1. Field of the Invention
The present invention relates to a bus bridge device that connects a first device executing a first process and a second device executing a second process in response to a request from the first device.
2. Description of the Related Art
Conventionally, when there is a necessity to carry out communication between a plurality of devices connected to a plurality of buses, the buses are connected by means of bus bridges to enable communication between the devices.
FIG. 5 is a drawing of a storage system that uses peripheral component interconnect (PCI) bridge modules and a packet network to connect PCI buses. As shown in FIG. 5, storage control modules 1001 and 1002 receive a processing request from hosts 101 and 102 and control a storage system 20. Disks 7001 and 7002 store data and cache memory modules 3001 through 3004 provide fast data access. Each of the storage control modules 1001 and 1002, the disks 7001 and 7002, and the cache memory modules 3001 through 3004 are connected to separate PCI buses 4001 through 4008. The PCI buses 4001 through 4008 are connected to a packet network 500 via PCI bridge modules 8001 through 8008.
When writing data to the storage system 20, for example, the storage control module 1001, upon fetching a write data request from the host 101, sends the write data request to the PCI bridge module 8001 via the PCI bus 4001. The PCI bridge module 8001 transmits the write data request to the PCI bridge module 8002 via the packet network 500, and the PCI bridge module 8002 sends the write data request to the cache memory module 3001 via the PCI bus 4002. The cache memory module 3001 writes data to a cache memory.
The storage control module 1001 also sends the write data request to the cache memory module 3002 via the PCI bridge module 8001, the packet network 500, and the PCI bridge module 8004 as a precaution against a breakdown of the cache memory module 3001.
The data written to the cache memory by the cache memory module 3001 and the cache memory module 3002 is later sent to a disk controller 6001 or a disk controller 6002, and written to the disk 7001 or the disk 7002.
Thus, in the storage system 20, the storage control module 1001 needs to send the write data request to the cache memory module 3001 connected to the PCI bus 4002 and the cache memory module 3002 connected to the PCI bus 4004.
FIG. 6 is a flowchart of a sequence of writing data to the cache memory by the storage system 20 shown in FIG. 5. As shown in FIG. 6, the storage control module 1001, when writing data to the cache memory module 3001, issues a write command (step S601). The PCI bridge module 8001, which fetches the write command, sets a transmission notifying register 250 that indicates that data is being transmitted (step S602), and packet transmits the write command to the PCI bridge module 8002 by means of the packet network 500 (step S603).
The PCI bridge module 8002 fetches the packet and issues a write command to the cache memory module 3001 (step S604). The cache memory module 3001 writes data to the cache memory (step S605). The cache memory module 3001 issues a reply code, which indicates a result of writing data (step S606). The PCI bridge module 8002, which fetches the reply code, packet transmits the reply code to the PCI bridge module 8001 by means of the packet network 500. The PCI bridge module 8001, upon fetching the reply code, sets a reply code notifying register 260 that indicates a receipt of the reply code (step S607), and resets the transmission notifying register 250 (step S608).
The storage control module 1001, upon issuing the write command, issues a validate command to the PCI bridge module 8001 to fetch the reply code (step S609). If the PCI bridge module 8001 has not received the reply code, the PCI bridge module 8001 sends a retry message to the storage control module 1001 to once again request issue of the validate command (step S610). Issue of a validate command by the storage control module 1001 and sending of a retry message by the PCI bridge module 8001 is repeated.
Next, when the PCI bridge module 8001 fetches the reply code and the storage control module 1001 issues a validate command (step S611), the PCI bridge module 8001 sends the reply code to the storage control module 1001 (step S612).
Thus, the conventional PCI bridge module 8001, by returning the reply code fetched from the PCI bridge module 8002 in response to a validate command issued by the storage control module 1001, notifies the storage control module 1001 of the status of writing data to the cache memory module 3001 connected to the other PCI bus 4002 (see Japanese Patent Laid-Open Publication No. 2001-243206). Specifications of a PCI bus are disclosed in “PCI Local Bus Specification Rev2.2 1998/12/18” (PCI Special Interest Group).
However, in the conventional technology, the storage control module 1001, which is a processing request source, is unable to carry out any other process until the receipt of the reply code. In other words, the storage control module 1001, which is the processing request source, needs to continuously issue a validate command during the time interval when the storage control module 1001 is fetching the retry message. Thus, unnecessary operation is repeated until the storage control module 1001 fetches the reply code.